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1

Vorbehaltlose Grundrechte am Beispiel des Schächtens

Georg Eggersglüss

Journal:

Zeitschrift für Rechtspolitik

Year:

1992

Language:

german

File:

PDF, 333 KB

german, 1992

2

[IEEE 2010 IEEE International Symposium on Circuits and Systems. ISCAS 2010 - Paris (2010.05.30-2010.06.2)] Proceedings of 2010 IEEE International Symposium on Circuits and Systems - Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation

Eggersgluss, Stephan, Tille, D, Drechsler, R

Year:

2010

Language:

english

File:

PDF, 180 KB

english, 2010

3

[IEEE 2007 IEEE International Symposium on Circuits and Systems - New Orleans, LA (2007.05.27-2007.05.30)] 2007 IEEE International Symposium on Circuits and Systems - SAT-based ATPG for Path Delay Faults in Sequential Circuits

Eggersgluss, S., Fey, G., Drechsler, R.

Year:

2007

Language:

english

File:

PDF, 231 KB

english, 2007

4

Organische Peroxyde (Auszug)

Dr.-Ing. G. W. Eggersglüss

Journal:

Angewandte Chemie

Year:

1950

Language:

german

File:

PDF, 291 KB

german, 1950

5

Fundamentals towards a Modular Microstructured Production Plant

Christoph Helling, Holger Fröhlich, Jan Eggersglüss, Prof. Dr. Jochen Strube

Journal:

Chemie Ingenieur Technik

Year:

2012

Language:

english

File:

PDF, 636 KB

english, 2012

6

On Acceleration of SAT-Based ATPG for Industrial Designs

Drechsler, R., Eggersgluss, S., Fey, G., Glowatz, A., Hapke, F., Schloeffel, J., Tille, D.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2008

Language:

english

File:

PDF, 266 KB

english, 2008

7

Incremental Solving Techniques for SAT-based ATPG

Tille, D., Eggersgluss, S., Drechsler, R.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2010

Language:

english

File:

PDF, 1.46 MB

english, 2010

8

Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application

Eggersgluss, S., Drechsler, R.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2011

Language:

english

File:

PDF, 602 KB

english, 2011

9

[IEEE 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC) - Florianopolis, Brazil (2009.10.12-2009.10.14)] 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC) - Structural heuristics for SAT-based ATPG

Tille, Daniel, Eggersgluss, Stephan, Le, Hoang M., Drechsler, Rolf

Year:

2009

Language:

english

File:

PDF, 127 KB

english, 2009

10

[IEEE 37th International Symposium on Multiple-Valued Logic - Oslo, Norway (2007.05.13-2007.05.16)] 37th International Symposium on Multiple-Valued Logic (ISMVL'07) - Experimental Studies on SAT-Based ATPG for Gate Delay Faults

Eggersgluss, Stephan, Tille, Daniel, Fey, Gorschwin, Drechsler, Rolf, Glowatz, Andreas, Hapke, Friedrich, Schloffel, Jurgen

Year:

2007

Language:

english

File:

PDF, 191 KB

english, 2007

11

[IEEE 2007 IFIP International Conference on Very Large Scale Integration - Atlanta, GA, USA (2007.10.15-2007.10.17)] 2007 IFIP International Conference on Very Large Scale Integration - SWORD: A SAT like prover using word level information

Wille, Robert, Fey, Gorschwin, Grobe, Daniel, Eggersgluss, Stephan, Drechsler, Rolf

Year:

2007

Language:

english

File:

PDF, 114 KB

english, 2007

12

[IEEE 38th International Symposium on Multiple Valued Logic - Dallas, TX (2008.05.22-2008.05.24)] 38th International Symposium on Multiple Valued Logic (ismvl 2008) - On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults

Eggersgluss, S., Drechsler, R.

Year:

2008

Language:

english

File:

PDF, 707 KB

english, 2008

13

[IEEE 2013 22nd Asian Test Symposium (ATS) - Yilan County, Taiwan (2013.11.18-2013.11.21)] 2013 22nd Asian Test Symposium - Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill

Eggersgluss, Stephan

Year:

2013

Language:

english

File:

PDF, 244 KB

english, 2013

14

[IEEE 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) - Nice (2007.05.30-2007.06.2)] 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007) - Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults

Eggersgluss, S., Fey, G., Drechsler, R., Glowatz, A., Hapke, F., Schloeffel, J.

Year:

2007

Language:

english

File:

PDF, 122 KB

english, 2007

15

[IEEE 2013 14th Latin American Test Workshop - LATW - Cordoba (2013.04.3-2013.04.5)] 2013 14th Latin American Test Workshop - LATW - PASSAT 2.0: A multi-functional SAT-based testing framework

Drechsler, Rolf, Diepenbeck, Melanie, Eggersgluss, Stephan, Wille, Robert

Year:

2013

Language:

english

File:

PDF, 68 KB

english, 2013

16

[IEEE 2014 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) - Santorini, Greece (2014.5.6-2014.5.8)] 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) - Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

Becker, Bernd, Drechsler, Rolf, Eggersgluss, Stephan, Sauer, Matthias

Year:

2014

Language:

english

File:

PDF, 532 KB

english, 2014

17

[IEEE 2012 21st Asian Test Symposium (ATS) - Niigata, Japan (2012.11.19-2012.11.22)] 2012 IEEE 21st Asian Test Symposium - Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization

Eggersgluss, Stephan, Yilmaz, Mahmut, Chakrabarty, Krishnendu

Year:

2012

Language:

english

File:

PDF, 194 KB

english, 2012

18

[IEEE 2010 15th IEEE European Test Symposium (ETS 2010) - Praha (2010.05.24-2010.05.28)] 2010 15th IEEE European Test Symposium - Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs

Tille, Daniel, Eggersgluss, Stephan, Krenz-Baath, Rene, Schloeffel, Juergen, Drechsler, Rolf

Year:

2010

Language:

english

File:

PDF, 352 KB

english, 2010

19

[IEEE 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) - San Jose, CA, USA (2013.11.18-2013.11.21)] 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) - Improved SAT-based ATPG: More constraints, better compaction

Eggersgluss, Stephan, Wille, Robert, Drechsler, Rolf

Year:

2013

Language:

english

File:

PDF, 665 KB

english, 2013

20

[IEEE 2009 14th IEEE European Test Symposium (ETS) - Sevilla, Spain (2009.05.25-2009.05.29)] 2009 14th IEEE European Test Symposium - Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques

Eggersgluss, Stephan, Drechsler, Rolf

Year:

2009

Language:

english

File:

PDF, 196 KB

english, 2009

21

[IEEE 2010 IEEE International Test Conference (ITC) - Austin, TX, USA (2010.11.2-2010.11.4)] 2010 IEEE International Test Conference - Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability

Eggersgluss, Stephan, Drechsler, Rolf

Year:

2010

Language:

english

File:

PDF, 216 KB

english, 2010

22

[IEEE 2016 IEEE European Test Symposium (ETS) - Amsterdam, Netherlands (2016.5.23-2016.5.27)] 2016 21th IEEE European Test Symposium (ETS) - SAT-based post-processing for regional capture power reduction in at-speed scan test generation

Eggersgluss, Stephan, Miyase, Kohei, Wen, Xiaoqing

Year:

2016

Language:

english

File:

PDF, 374 KB

english, 2016

23

[IEEE 2016 IEEE European Test Symposium (ETS) - Amsterdam, Netherlands (2016.5.23-2016.5.27)] 2016 21th IEEE European Test Symposium (ETS) - VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers

Huhn, Sebastian, Eggersgluss, Stephan, Drechsler, Rolf

Year:

2016

Language:

english

File:

PDF, 367 KB

english, 2016

24

[IEEE 2017 22nd IEEE European Test Symposium (ETS) - Limassol, Cyprus (2017.5.22-2017.5.26)] 2017 22nd IEEE European Test Symposium (ETS) - Foreword

Michael, Maria K., Drechsler, Rolf, Eggersgluss, Stephan, Stratigopoulos, Haralampos-G., Hellebrand, Sybille, Aitken, Rob

Year:

2017

File:

PDF, 57 KB

2017

25

[IEEE 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Budapest, Hungary (2018.4.25-2018.4.27)] 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing

Dhotre, Harshad, Eggersgluss, Stephan, Drechsler, Rolf, Dehbashi, Mehdi, Pfannkuchen, Ulrike

Year:

2018

Language:

english

File:

PDF, 613 KB

english, 2018

26

[IEEE 2019 IEEE International Test Conference (ITC) - Washington, DC, USA (2019.11.9-2019.11.15)] 2019 IEEE International Test Conference (ITC) - Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques

Eggersgluss, Stephan

Year:

2019

Language:

english

File:

PDF, 2.63 MB

english, 2019

27

[IEEE 2019 IEEE International Test Conference (ITC) - Washington, DC, USA (2019.11.9-2019.11.15)] 2019 IEEE International Test Conference (ITC) - IEEE European Test Symposium (ETS)

Eggersgluss, Stephan, Hamdioui, Said, Jutman, Artur, Michael, Maria K., Raik, Jaan, Reorda, Matteo Sonza, Tahoori, Mehdi, Vatajelu, Elena-Ioana

Year:

2019

Language:

english

File:

PDF, 8.29 MB

english, 2019